The structure of a conventional liquid crystal electrooptical device is shown in FIG. 10.
In FIG. 10, the liquid crystal electrooptical device, indicated by numeral 1001, consists principally of a signal line driver portion 1015, a gate driver portion 1016, and an m.times.n pixel matrix 1005 (pixels arranged in m rows and n columns).
The signal line driver portion 1015 is composed of source-side shift registers 1002 and a sample-and-hold circuit 1003 for sampling a video signal. The shift registers 1002 are made from complementary TFTs. Similarly, the sample-and-hold circuit 1003 is made of complementary TFTs.
The gate driver portion 1016 is composed of gate-side shift registers 1006 and a buffer circuit 1007. The shift registers 1006 are made of complementary TFTs. Similarly, the buffer circuit 1007 consists of complementary TFTs.
The pixel matrix portion 1005 comprises the pixels 1004 arranged in rows and columns on a plane.
FIG. 2 shows the circuit configuration of each pixel. Each pixel is composed of an N-channel TFT (thin-film transistor) 200, a liquid crystal element 204, and an auxiliary capacitor 206.
The N-channel TFT 200 has a drain electrode 203 to which the liquid crystal element 204 and the auxiliary capacitor 206 are connected. A counter electrode 205 is connected with the side of the liquid-crystal element opposite to the drain. The electrode 207 of the auxiliary capacitor on the opposite side of the drain is grounded.
Referring back to FIG. 10, the pixel matrix 1005 includes the individual pixels 1004. Source signal lines or signal lines 1009 are each connected with the source electrode 201 shown in FIG. 2. Gate signal lines or scanning lines 1008 are each connected with the gate electrode 202 shown in FIG. 2.
The arrangement of the pixels in the pixel matrix 1005 is described now. M source signal lines 1009 extend vertically and are connected with the signal line driver 1015. The source electrodes 201 of the individual TFTs of the n pixels 1004 are connected with the source signal lines, respectively.
N scanning lines 1008 extend horizontally. The gate electrodes 202 of the individual TFTs of the m pixels 1004 are connected with the gate signal lines 1008, respectively.
In the signal line driver circuit 1015, a source signal (display signal) start signal line 1010 and a source line-side (signal line-side) shift clock 1011 are connected as external terminals with the source line-side (signal line-side) shift registers 1002. An image data signal line 1012 is connected as an external terminal with the sample-and-hold circuit.
The operation of the conventional structure is next described.
First, an operation for activating pixels connected with one gate signal line (scanning line) is described.
The i-th line in the vertical direction (hereinafter referred to as the i-th line) is discussed. When the gate signal line (scanning line) 1008 on the i-th line goes high, the gate electrodes 202 of all the pixels 1004 on the i-th line are activated. An electrical conduction occurs between the source 201 and the drain 203 of each of all the TFTs 200 on the i-th line.
In response to both signal line start signal 1010 and source-side shift clock 1011, the sample-and-hold circuit samples a video signal, or a sampled signal 1017, from the left end of the i-th line. The display signal is written to the successive pixels. Thus, writing for one line is completed.
An operation for displaying one frame of image is described below.
A gate start signal 1013 and a gate-side shift clock 1014 make the gate signal on the vertically top line go high. This signal is shifted downward by the gate-side shift clock 1014.
The above-described principle of operation for 1 line is executed when the gate signal of each line is high (H). In this way, one frame of image is displayed.
The state of the polarity of the display signal for one frame of image is shown in FIG. 3.
When one frame of image is displayed, in order to prevent flicker, the polarity of the source signal (display signal) supplied from the source signal line 1009 is inverted between adjacent lines, i.e., between the i-th line and the (i+1)th line, as shown in FIG. 3. This is referred to as line inversion. In other words, the polarity of the display signal for the odd-numbered ((2i-1)th) line is opposite to the polarity of the even-numbered (2i-th) line.
This is accomplished by supplying the image data signal applied from the image data signal line 1012 in such a way that the polarity is inverted from one line to an adjacent line.
With respect to one line, the polarity is inverted every frame to prevent the liquid crystal from deteriorating.
The input image data used by the conventional device is shown in FIG. 11.
The present invention is intended to provide techniques for reducing the electric power consumed by a liquid crystal electrooptical device when it is in operation. The problems with the conventional device are next described.
To prevent the liquid crystal electrooptical device from producing flicker, the polarity of the image data signal is inverted from line to line, as described in connection with the conventional structure and operation.
However, the electric power consumed when the liquid crystal electrooptical device is operated is increased by the fact that the image data signal is inverted between adjacent lines.
The image data signal is inverted between adjacent lines. This increases the amount of electric power consumed by the liquid crystal electrooptical device. This is briefly described by referring to FIGS. 10 and 2.
Referring to FIG. 2, Let Con be the pixel capacitance when the N-type TFT 200 is conducting. Let Coff be the pixel capacitance when the N-type TFT 200 is cutoff. Referring to FIG. 10, let Cl be the capacitance of one vertically extending source signal line 1009 of the liquid crystal electrooptical device 1001. Let V be the voltage for activating one liquid crystal element. The voltage on the positive polarity side is V/2. The voltage on the negative polarity side is V/2. Let F1 be the number of line inversions. It is assumed that an m.times.n matrix structure is formed. In order to activate one source signal line 1009 extending vertically, electric power given by EQU Wl=(Cl+Con+Coff+(n-1)).times.V.times.V.times.Fl (A)
is required. Therefore, an electric power W.sub.1 given by EQU W.sub.1 =m.times.Wl (B)
is necessary to display one frame of image.
The problem is that the device is driven with line inversion. Since the number of line inversions Fl is substantially equal to the number of lines, i.e., the gate signal lines (scanning lines). Therefore, for a general display device, about 400 to 500 line inversions take place per frame of image.
If no line inversion is done, the electric power consumption accompanying inversion of the polarity of the display signal occurs only when the polarity is inverted every frame in order to prevent deterioration of the liquid crystal. That is, the electric power is consumed whenever the frame is inverted, i.e., every frame of image. Letting Ff be the number of frame inversions, the total electric power consumed during display is given by EQU W.sub.a =(Cl+Con+Coff.times.(n-1)).times.V.times.V.times.m.times.Ff(C)
The electric power consumed during one frame is given when Ff=1 in the Eq. (C). Accordingly, if only frame inversion is done, the amount of electric power consumed by the pixel matrix portion is reduced by a factor equal to the line inversion number compared with the case in which line inversions are done. Hence, the amount of electric power can be decreased greatly.
Furthermore, the amounts of electric power consumed by the sample-and-hold circuit, an analog buffer circuit, and other circuits of the driver circuit portion can be reduced greatly as well as the electric power consumed by the pixel matrix portion, by not adopting the line inversion method.
However, if the line inversion method is not executed, and if only the frame inversion method is conducted (i.e., the polarity of the display signal is inverted every frame), then flicker is produced. This deteriorates the image quality severely.
Another method of decreasing the amount of electric power consumed is to reduce the amounts of electric power consumed by the source-side shift registers 1001, by the gate-side shift registers 1006, and by the gate electrode-side buffer 1007. However, the amount of reduction achieved is small compared with the total amount of electric power consumed.
In the Eq. (A) above, only the interconnect capacitance is taken into account. A further method of reducing the interconnect capacitance is to thin the interconnects.
However, if the interconnects are thinned, the interconnect resistance is increased. Furthermore, the design rules impose limitations on this method.
If the interconnects are made thicker to reduce the interconnect resistance, the interconnect capacitance is increased. Moreover, the pixel spacing is increased. This lowers the aperture ratio, thus adversely affecting the image quality.
As can be readily understood from the Eq. (A), the simplest efficient method for reducing electric power consumed is to lower the driving voltage V. However, where good image quality and display speed are also taken into consideration, it cannot be said that this is a practical method.